The inventive concepts described herein relate to a device and a method of testing a digital logic circuit, and more particularly to an unbalanced multiplexer usable for a scan test and a scan flip-flop applying the unbalanced multiplexer.
Design for testability (DFT) technology for testing a semiconductor chip may be widely used to maintain quality of the semiconductor chip. Scan test technology using a flip-flop may typically be used to enable low cost testing. Research has recently focused on reducing power consumption of semiconductor chips. Accordingly, scan test technology capable of stably testing semiconductor chips at a low voltage is needed.